• It is similar to cellular automata, but eliminates the unphysical need for a global clock, and does not require many cells for logic or deterministic asynchronous operation.
• It is a Petri Net on a lattice with nearest-neighbor connections.
• It is a form of RISC, where the instructions are reduced to a single logical operation.
• It is a multicore processor that effectively has a core for every bit.
• It is a field-programmable gate array with single-gate logic blocks and nearest-neighbor switch matrices; it does not need a clock, because of its homogeneity a fitter is not needed to map a logic diagram onto corresponding device resources, and a larger program can transparently be distributed across multiple smaller chips.
• It is a systolic array that allows for arbitrary data flow and logic.
• It is a form of dataflow programming in which the graph itself is executable, without requiring event scheduling.
• It is a form of reconfigurable asynchronous logic in which a logical specification is equal to its asynchronous implementation because each gate implements deterministic asynchronous operation.
What it is? It's RALA: Reconfigurable Asynchronous Logic Automata